Carrier for double-side polishing apparatus, double-side polishing apparatus using the same, and double-side polishing method

ABSTRACT

The present invention provides a carrier for double-side polishing apparatus which is set between upper and lower turn tables having polishing pads attached thereto and has a holding hole in which a semiconductor wafer sandwiched between the upper and lower turn tables is held at the time of polishing in a double-side polishing apparatus, wherein a material of the carrier is titanium, and surface roughness of the titanium carrier is 0.14 μm or above in terms of Ra. As a result, there can be provided the carrier for double-side polishing apparatus, a double-side polishing apparatus, and a double-side polishing method that can stably and efficiently produce a high-quality wafer having reduced wafer peripheral sag and a high flatness at the time of double-side polishing of a semiconductor wafer.

TECHNICAL FIELD

The present invention relates to a carrier for double-side polishingapparatus that holds a semiconductor wafer when polishing thesemiconductor wafer in a double-side polishing apparatus.

BACKGROUND ART

When, e.g., polishing both surfaces of a semiconductor wafer, thesemiconductor wafer is held by a carrier in conventional examples. Thiscarrier is formed with a thickness thinner than that of thesemiconductor wafer and has a wafer holding hole through which the waferis held at a predetermined position between an upper turn table and alower turn table of a double-side polishing apparatus. The semiconductorwafer is inserted into and held in this wafer holding hole, upper andlower surfaces of the semiconductor wafer are sandwiched by polishingjig, e.g., polishing pads provided on opposed surfaces of the upper turntable and the lower turn table, and polishing is carried out whilesupplying a polishing agent to the polishing target surfaces.

When double-side polishing is carried out in this manner, an outerperipheral portion alone of the semiconductor wafer is excessivelypolished due to, e.g., concentration of a pressure on the outerperipheral portion of the semiconductor wafer or an influence ofviscoelasticity of a polishing slurry or polishing pads, and peripheralsag occurs. There is a problem that this peripheral sag degrades aflatness of the wafer.

As a method for reducing such peripheral sag, there is disclosed amethod for performing a secondary double-side polishing step thatremedies peripheral sag produced at a primary double-side polishing step(see Japanese Unexamined Patent Publication (Kokai) No. 2005-158798).

However, this method has a defect that the number of steps is increasedwhen the secondary double-side polishing step that remedies theperipheral sag is performed, and a double-side polishing method that canmore readily reduce the peripheral sag has been demanded.

Further, in conventional wafer polishing, dressing of polishing padsurfaces is performed by using, e.g., a ceramic plate in order to obtainstable polishing characteristics. However, in the double-side polishing,not only the wafer as a workpiece but also a carrier is in contact withthe polishing pads, an effect of dressing of the polishing pad surfacesdoes not last long, and there is a problem that dressing of thepolishing pad surfaces must be frequently carried out by using, e.g., aceramic plate.

Furthermore, there is also a problem that a life of the carrier itselfis short and a cost is increased.

DISCLOSURE OF INVENTION

Therefore, in view of the above-explained problems, it is an object ofthe present invention to provide a carrier for double-side polishingapparatus that enables stably and efficiently producing a high-qualitywafer having a high flatness with reduced wafer peripheral sag at a lowcost at the time of double-side polishing of the semiconductor wafer, adouble-side polishing apparatus using the same, and a double-sidepolishing method.

To achieve this object, according to the present invention, there isprovided a carrier for double-side polishing apparatus which is setbetween upper and lower turn tables having polishing pads attachedthereto and has a holding hole in which a semiconductor wafer sandwichedbetween the upper and lower turn tables is held at the time of polishingin a double-side polishing apparatus, wherein a material of the carrieris titanium, and surface roughness of the titanium carrier is 0.14 μm orabove in terms of Ra.

When the material of the carrier is titanium, since a hardness is higherand abrasion at the time of polishing is smaller than those of a resin,a carrier life can be improved. Furthermore, titanium itself has a smalldiffusion coefficient in the semiconductor wafer, e.g., silicon, ithardly becomes a problem as an impurity, and a metal impurity having alarge diffusion coefficient like Fe is not present in titanium, therebysuppressing contamination of the metal impurity with respect to thesemiconductor wafer. Moreover, when such a titanium carrier havingsurface roughness of 0.14 μm or above in terms of Ra is used, thehigh-quality wafer having reduced peripheral sag and a high flatness canbe stably efficiently produced. Additionally, since dressing of thepolishing pads can be performed by using the carrier surface duringpolishing, a frequency of dressing of the polishing pads using, e.g.,ceramic plate can be reduced, thus efficient polishing can be performed.

At this time, it is preferable for the surface roughness to be 0.32 μmor above in terms of Ra.

When the surface roughness of the carrier is 0.32 μm or above in termsof Ra, the high-quality wafer having reduced peripheral sag and a highflatness can be produced.

Moreover, it is preferable that the carrier to have grooves eachreaching the holding hole from a carrier outer peripheral side on frontand back surfaces thereof.

When the carrier has the grooves each reaching the holding hole from thecarrier outer peripheral side on front and back surfaces thereof in thismanner, since the polishing liquid is supplied to the semiconductorwafer through the grooves at the time of polishing, a resistanceundergone by the wafer outer peripheral portion at the time of polishingcan be alleviated, and the peripheral sag can be reduced. Additionally,dressing of the polishing pads can be also performed by the grooveduring polishing, a frequency of dressing of the polishing pads using,e.g., ceramic plate can be further decreased.

Further, a pattern of the grooves can be a grid-like pattern or a radialpattern.

When the pattern of the grooves is the grid-like pattern or the radialpattern in this manner, the polishing liquid can be easily and assuredlysupplied to the semiconductor wafer at the time of polishing.

Furthermore, when a double-side polishing apparatus comprising at leastthe carrier for double-side polishing apparatus according to the presentinvention is provided, since the material of the carrier is titanium, alife can be increased, and contamination of a metal impurity withrespect to a semiconductor wafer can be suppressed, thereby producingthe high-quality wafer having reduced peripheral sag and a highflatness. Moreover, since dressing of polishing pads can be performed bycarrier surfaces during polishing, a frequency of dressing of thepolishing pads using, e.g., ceramic plate can be reduced, thusconsiderably improving an operating rate of the apparatus.

Furthermore, there is provided a double-side polishing method for asemiconductor wafer, comprising: arranging the carrier between upper andlower turn tables holding the semiconductor wafer in a holding holeformed in the carrier; and sandwiching the semiconductor wafer betweenthe upper and lower turn tables to perform double-side polishing.

When the semiconductor wafer is held in the holding hole of the carrierfor double-side polishing apparatus and sandwiched between the upper andlower turn tables to perform double-side polishing in this manner, alife of the carrier is increased, and the high-quality wafer havingreduced contamination due to a metal impurity, decreased peripheral sagand a high flatness can be produced. Moreover, dressing of the polishingpads using the carrier surfaces can be carried out during polishing.Therefore, a frequency of dressing of the polishing pads using, e.g.,ceramic plate can be reduced, a cost can be decreased, and thesemiconductor wafer can be efficiently subjected to double-sidepolishing.

As explained above, according to the present invention, since titaniumis adopted as the material, the carrier for double-side polishingapparatus that has an improved life and hardly occurs contamination dueto a metal impurity can be provided, and the high-quality wafer havingreduced contamination due to the metal impurity, and decreasedperipheral sag, and a high flatness can be stably efficiently producedby using this carrier. Moreover, since dressing of the polishing padscan be performed by using the carrier surfaces during polishing, afrequency of dressing of the polishing pads using, e.g., a ceramic platecan be reduced. Therefore, a cost can be reduced, and the semiconductorwafer can be efficiently subjected to double-side polishing.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a vertical cross-sectional view showing an example of adouble-side polishing apparatus including a carrier for double-sideapparatus according to the present invention;

FIG. 2 is an internal structural view of the double-side polishingapparatus as seen from a plane;

FIG. 3 is a schematic view showing a measurement position for aperipheral sag amount;

FIG. 4 shows measurement results of experiments;

FIG. 5 shows measurement results of experiments;

FIG. 6 show an example of a pattern of grooves on front and backsurfaces of the carrier for double-side polishing apparatus according tothe present invention, (a) grid-like pattern, (b) radial pattern;

FIG. 7 shows measurement results of Examples 1 and 2 and ComparativeExamples 1 and 2;

FIG. 8 shows measurement results of Examples 3 to 7; and

FIG. 9 shows measurement results of Example 8 and Comparative Example 3.

BEST MODE(S) FOR CARRYING OUT THE INVENTION

An embodiment according to the present invention will now be explainedhereinafter, the present invention is not restricted thereto.

As a conventional carrier for double-side polishing apparatus, there isone formed of a metal, e.g., stainless or one having ceramic abrasivegrains deposited on a surface of a metal plate, for example. However,when such carriers are used, an outer peripheral portion alone of a heldsemiconductor wafer is excessively polished at the time of polishing tocause peripheral sag, or deposited abrasive grains fall off to producescratches on a wafer surface, resulting in a problem that a quality ofthe semiconductor wafer is reduced.

Further, in double-side polishing, there is a problem that an effect ofdressing of polishing pad surfaces does not last long and a ceramicplate or the like must be frequently used to perform dressing of thepolishing pad surfaces.

Thus, as a result of keenly conducting experiments, the present inventorhas found that a carrier for double-side polishing apparatus in which amaterial of the carrier is titanium and surface roughness of thetitanium carrier is 0.14 μm or above in terms of Ra can solve theabove-explained problem, thereby bringing the present invention tocompletion.

That is, when such a carrier for double-side polishing apparatus is usedto perform double-side polishing, a high-quality wafer having reducedperipheral sag and a high flatness can be produced. Furthermore, sincedressing of the polishing pads can be performed by using carriersurfaces during polishing, a frequency of dressing of the polishing padsusing, e.g., ceramic plate can be reduced, and polishing can beefficiently carried out. Moreover, this carrier has a structure whereeach carrier surface itself is roughened without depositing abrasivegrains, the abrasive grains do not fall off to produce scratches on thewafer surfaces. Additionally, since titanium is adopted as the material,a life becomes long, and contamination of, e.g., iron that affects awafer quality does not occur.

An embodiment according to the present invention will now be explainedhereinafter with reference to appended drawings.

Here, FIG. 1 is a vertical cross-sectional view showing an example of adouble-side polishing apparatus including a double-side polishingapparatus according to the present invention, and FIG. 2 is an internalstructural view of the double-side polishing apparatus as seen from aplane.

The present invention relates to an improvement in a carrier that holdsa semiconductor wafer in a double-side polishing apparatus thatsimultaneously polishes both surfaces of the semiconductor wafer, and anoutline of the double-side polishing apparatus will be first explainedwith reference to FIGS. 1 and 2.

A double-side polishing apparatus 11 provided with a carrier 10 fordouble-side polishing apparatus includes a lower turn table 12 and anupper turn table 13 vertically provided to face each other, andpolishing pads 14 are attached to opposed surfaces sides of therespective turn tables 12 and 13. Further, a sun gear 15 is provided ata central portion between the upper turntable 13 and the lower turntable12, and an internal gear 16 is provided at a rim portion. Asemiconductor wafer W is held in a holding hole 17 of the carrier 10 andsandwiched between the upper turntable 13 and the lower turn table 12.

Outer peripheral teeth of each carrier 10 mesh with respective toothportions of the sun gear 15 and the internal gear 16, and each carrier10 rotates around the sun gear 15 while rotating on its axis when theupper turn table 13 and the lower turn table 12 are rotated by anon-illustrated driving source. At this time, each semiconductor wafer Wis held in the holding hole 17 of the carrier 10, and both surfacesthereof are simultaneously polished by the upper and lower polishingpads 14. At the time of polishing, a polishing liquid is supplied from anon-illustrated nozzle.

It is to be noted that each carrier holds one wafer to perform polishingin FIG. 2, but carriers each having a number of holding holes may beused and a number of wafers may be held in each carrier to performpolishing.

The carrier 10 for double-side polishing apparatus according to thepresent invention set in the double-side polishing apparatus 11 will nowbe explained hereinafter.

A material of the carrier 10 according to the present invention istitanium, and this material has a higher hardness than that a SUSmaterial coated with resin and does not have an impurity with a largediffusion coefficient like Fe or Ni contained therein. Therefore,scratches or damages can be reduced to increase a carrier life, and acost can be reduced. Furthermore, contamination of a metal that becomesa problem of the semiconductor wafer W can be suppressed.

A hardness of SUS as a conventional carrier material is 420 Hv, and ahardness of Ti as a material of the carrier 10 according to the presentinvention is 220 Hv. Therefore, it has been conventionally consideredthat Ti has the hardness lower than that of SUS and cannot be used as amaterial of the carrier. However, as explained above, a carrier havingthe exposed SUS material causes occurrence of crucial metalcontamination with respect to the semiconductor wafer W, and the SUSmaterial must be actually coated with a resin in order to suppress themetal contamination. Therefore, each surface of the carrier 10 accordingto the present invention is titanium, as its material is harder thaneach surface of the conventional carrier coated with a resin. Therefore,its life becomes long.

Moreover, the carrier 10 according to the present invention is featuredin that its surface roughness is 0.14 μm or above in terms of Ra. As aresult of conducting the following experiment, the present inventor hasdiscovered that the surface roughness of the carrier must be 0.14 μm orabove in terms of Ra in order to obtain a wafer having reducedperipheral sag.

(Experiment)

As the carrier for double-side polishing apparatus, a number of carrierswhich are formed of titanium and have different surface roughnessdegrees obtained by roughening front and back surfaces thereof bydiamond pellets having different sizes were prepared.

The surface roughness of each carrier surface was measured by using SurfTest SJ-201P manufactured by Mitutoyo, and evaluation was carried outbased on JIS B0601-1994.

Each of the carriers was set in a double-side polishing apparatus,dressing of polishing pads was performed, and then double-side polishingof each silicon wafer having a diameter of 300 mm was performed. Thatis, the etched silicon wafer was set in each of five titanium carrierseach having one holding hole, an upper turn table was rotated in aclockwise direction whilst a lower turn table was rotated in acounterclockwise direction with a number of revolutions of 20 rpm and aload of 250 g/cm², and an alkaline solution containing colloidal silicawas used as a polishing liquid to perform polishing.

A peripheral sag amount of each polished wafer was measured. A wafershape evaluation apparatus manufactured by Kuroda Precision IndustriesLtd. was used to measure a difference in wafer shape between a positionthat is 1 mm away from a wafer edge and a position that is 3 mm awayfrom the same as a peripheral sag amount with a section between aposition that is 30 mm away from the wafer edge and a position whereperipheral sag starts being determined as a reference plane as shown inFIG. 3. The following Table 1 and FIGS. 4 and 5 show measurementresults.

TABLE 1 Carrier surface Peripheral sag roughness (Ra: μm) amount (μm)0.03 0.162 0.08 0.154 0.14 0.099 0.24 0.068 0.32 0.059 0.50 0.061

As is obvious from Table 1 and FIGS. 4 and 5, it can be understood thatsetting roughness of each carrier surface to 0.14 μm or above in termsof Ra enables considerably improving the peripheral sag amount andobtaining each wafer having reduced peripheral sag and a high flatness.Further, it can be also understood that setting roughness of eachcarrier surface to 0.32 μm or above in terms of Ra enables furtherreducing the peripheral sag.

It is to be noted that, in this experiment, deformation or damages ofeach carrier do not occur even if the front and back surfaces of thecarrier are roughened, the carrier can be used to reach its lifeequivalent to that of a titanium carrier that is not subjected toprocessing of roughening the front and back surfaces of the carrier, andany difference in wafer quality other than a flatness from thenon-processed carrier was not recognized.

However, when roughness of each carrier surface becomes too high, it canbe considered that deformation or damages of the carrier are apt tooccur and the life of the carrier is reduced. Therefore, it is desirableto set roughness of each surface to 10 μm or below in terms of Ra.

Additionally, it has been revealed that dressing of the polishing padscan be performed during polishing by roughening the front and backsurfaces of the carrier. Although dressing is performed once in 10batches in conventional examples, the same effect can be obtained bycarrying out dressing once in 40 batches.

As explained above, the titanium carrier having surface roughness of0.14 μm or above in terms of Ra, or more preferably the titanium carrierhaving surface roughness of 0.32 μm or above in terms of Ra has a longcarrier life, and performing double-side polishing by using this carrierenables stably and efficiently producing a high-quality wafer havingreduced metal contamination, decreased peripheral sag, and a highflatness at a low cost. Further, since dressing of the polishing padscan be performed by using carrier surfaces during polishing, a frequencyof dressing of the polishing pads using, e.g., ceramic plate can bereduced, and an operating rate of the apparatus can be considerablyimproved.

Furthermore, it is preferable for the carrier according to the presentinvention to have grooves each reaching the holding hole from thecarrier outer peripheral side on the front and back surfaces thereof.When the carrier has such grooves, since the polishing liquid issupplied to the semiconductor wafer through the grooves at the time ofpolishing, a resistance undergone by the wafer outer peripheral portionat the time of polishing can be alleviated, thereby reducing theperipheral sag. Further, since dressing of the polishing pads can becarried out by using the grooves during polishing, a frequency ofdressing of the polishing pads using, e.g., ceramic plate can be furtherreduced.

Although a pattern of the grooves is not restricted in particular, itmay be, e.g., a grid-like pattern described in FIG. 6( a), a radialpattern grooves 18 shown in FIG. 6( b), or a pattern of horizontalstripes or vertical stripes.

Although a size of each groove 18 is not restricted in particular, thegroove 18 may have, e.g., a width of 1 to 2 mm and a depth of 2 to 6 μm.

It is to be noted that the planetary carrier for the double-sidepolishing apparatus has been taken as an example and explained, thecarrier for double-side polishing apparatus according to the presentinvention is not restricted to the planetary type, and it is alsoeffective to adopt a carrier for swinging type double-side polishingapparatus.

When the double-side polishing apparatus 11 provided with the carrier 10for the double-side polishing apparatus according to the presentinvention is adopted, a wafer having reduced metal contamination,decreased peripheral sag, and a high flatness can be obtained.Furthermore, since dressing of the polishing pads can be performed byusing the carrier surfaces during polishing, a frequency of dressing ofthe polishing pads can be reduced, and an operating rate of theapparatus can be considerably improved. Moreover, since a carrier lifeis long, a cost can be reduced.

Additionally, the carrier 10 for the double-side polishing apparatusaccording to the present invention can be set between the upper andlower turn tables 12 and 13 having the polishing pads 14 of thedouble-side polishing apparatus 11 attached thereto, the semiconductorwafer W is held in the holding hole 17 to be sandwiched between theupper and lower turn tables 12 and 13, and the wafer W can be subjectedto double-side polishing while supplying the polishing liquid.

When such a method is used to carry out double-side polishing, metalcontamination can be suppressed, and a wafer having reduced peripheralsag and a high flatness can be stably obtained. Further, since dressingof the polishing pads can be carried out by using the carrier surfacesduring polishing, a frequency of dressing of the polishing pads can bereduced, and polishing can be efficiently carried out. Furthermore,since each surface of the carried made of titanium itself haspredetermined roughness, a coating layer of, e.g., abrasive grains canbe prevented from being delaminated from each carrier surface to damagethe wafer.

The present invention will be described in detail below based onexamples and comparative examples. However, the present invention is notlimited thereto.

Examples 1 and 2

A double-side polishing apparatus 11 shown in FIGS. 1 and 2 wasprepared. Front and back surfaces of each titanium carrier 10 wereroughened by using a diamond pellet in advance. Surface roughness ofeach carrier surface was measured by using Surf Test SJ-201Pmanufactured by Mitutoyo, and evaluation was carried out based on JISB0601-1994. The surface roughness was Ra=0.28 to 0.32 μm (Examples 1 and2). This carrier 10 was used to perform double-side polishing asfollows.

After performing dressing of polishing pads 14, double-side polishing ofeach silicon wafer having a diameter of 300 mm was performed. That is,one etched silicon wafer W was set in each of five titanium carrierseach having a holding hole 17, an upper turn table 13 was rotated in aclockwise direction whilst a lower turn table 12 was rotated in acounterclockwise direction with a number of revolutions of 20 rpm and aload of 250 g/cm², and an alkaline solution containing colloidal silicawas used as a polishing liquid. This polishing was repeatedly performedfor four times.

A peripheral sag amount of each wafer after polishing was measured. Likethe above-explained experiment, a wafer shape evaluation apparatusmanufactured by Kuroda Precision Industries Ltd. was used to measure adifference in wafer shape between a position that is 1 mm away from awafer edge and a position that is 3 mm away from the same as aperipheral sag amount with a section from a position that is 30 mm apartform the wafer edge to a position where peripheral sag starts beingdetermined as a reference plane. FIG. 7 shows obtained measurementresults.

Comparative Examples 1 and 2

Double-side polishing and measurement were carried out under the sameconditions as those of (Examples 1 and 2) except that each titaniumcarrier (surface roughness was Ra=0.02 to 0.06 μm) having non-roughenedfront and back surfaces was used (Comparative Examples 1 and 2). FIG. 7shows obtained measurement results.

As shown in FIG. 7, it has been confirmed that, when the front and backsurfaces of each titanium carrier are roughened to have Ra of 0.14 μm orabove, each wafer having reduced peripheral sag and a high flatness canbe obtained in each of the four polishing operations.

Examples 3, 4, and 5

Like Examples 1 and 2, front and back surfaces of each titanium carrierwere roughened by using a diamond pellet (Ra=0.28 to 0.32 μm), and thengrooves having such a grid-like pattern as described in FIG. 6( a) wereformed. A groove width was 1 mm, a groove depth was 2 μm, and a grooveinterval was 2 mm. Double-side polishing was performed under the sameconditions as those of Examples 1 and 2 except that each carrier havingsuch grooves was used.

Further, a peripheral sag amount of each polished wafer was measuredlike Examples 1 and 2 (Examples 3, 4, and 5).

FIG. 8 shows obtained measurement results.

Examples 6 and 7

Double-side polishing and measurement were performed under the sameconditions as those of (Examples 3, 4, and 5) except that each titaniumcarrier having no groove formed thereon and Ra=0.28 to 0.32 μm was used(Examples 6 and 7). FIG. 8 shows obtained measurement results.

It can be understood from the measurement results of the peripheral sagamount described in FIG. 8 that each wafer according to Examples 3, 4,and 5 has a higher flatness than each wafer according to Examples 6 and7. In particular, it has been confirmed that the peripheral sag amountaccording to each of Examples 3, 4, and 5 is far smaller than thataccording to Examples 6 and 7 and the peripheral sag can be furtherimproved by forming the grooves on the carrier.

Example 8

Double-side polishing was performed under the same conditions as thoseof Examples 1 and 2. Surface roughness of each carrier having front andback surfaces roughened by a diamond pellet was Ra=0.28 to 0.32 μm.

Observing each polished wafer by using a wafer surface inspectionapparatus manufactured by Raytex Corporation, no scratch was observed oneach wafer surface (FIG. 9), and it has been confirmed that thehigh-quality wafer was obtained.

Comparative Example 3

Each surface of SUS carrier was subjected to blast processing to form anuneven surface having surface roughness Ra=4.8 to 5.0 μm. Ceramicabrasive grains were deposited on this uneven surface. Double-sidepolishing was carried out under the same conditions as those of Example8 except that such carrier was used.

Observing each polished wafer by using the wafer surface inspectionapparatus manufactured by Raytex Corporation, scratches were observed onthe wafer surface (FIG. 9). It can be considered that the abrasivegrains deposited on the carrier surfaces fell off to occur scratches onthe wafer surface during polishing.

When the carrier having abrasive grains deposited thereon is used inthis manner, a quality of a wafer may be possibly degraded, but usingthe carrier according to the present invention enables obtaining ahigh-quality wafer.

The present invention is not limited to the embodiment described above.The above-described aspects are mere examples and those havingsubstantially the same structure as technical ideas described in theappended claims and providing the similar functions and advantages areincluded in the scope of the present invention.

1. A carrier for double-side polishing apparatus which is set betweenupper and lower turn tables having polishing pads attached thereto andhas a holding hole in which a semiconductor wafer sandwiched between theupper and lower turn tables is held at the time of polishing in adouble-side polishing apparatus, wherein a material of the carrier istitanium, and surface roughness of the titanium carrier is 0.14 μm orabove in terms of Ra.
 2. The carrier for double-side polishing apparatusaccording to claim 1, wherein the surface roughness is 0.32 μm or abovein terms of Ra.
 3. The carrier for double-side polishing apparatusaccording to claim 1, wherein the carrier has grooves each reaching theholding hole from a carrier outer peripheral side on front and backsurfaces thereof.
 4. The carrier for double-side polishing apparatusaccording to claim 3, wherein a pattern of the grooves is a grid-likepattern or a radial pattern.
 5. A double-side polishing apparatuscomprising at least the carrier for double-side polishing apparatusaccording to claim
 1. 6. A double-side polishing method for asemiconductor wafer, comprising: arranging the carrier according toclaim 1 between upper and lower turn tables holding the semiconductorwafer in a holding hole formed in the carrier; and sandwiching thesemiconductor wafer between the upper and lower turn tables to performdouble-side polishing.
 7. The carrier for double-side polishingapparatus according to claim 2, wherein the carrier has grooves eachreaching the holding hole from a carrier outer peripheral side on frontand back surfaces thereof.
 8. The carrier for double-side polishingapparatus according to claim 7, wherein a pattern of the grooves is agrid-like pattern or a radial pattern.
 9. A double-side polishingapparatus comprising at least the carrier for double-side polishingapparatus according to claim
 2. 10. A double-side polishing apparatuscomprising at least the carrier for double-side polishing apparatusaccording to claim
 3. 11. A double-side polishing apparatus comprisingat least the carrier for double-side polishing apparatus according toclaim
 4. 12. A double-side polishing apparatus comprising at least thecarrier for double-side polishing apparatus according to claim
 7. 13. Adouble-side polishing apparatus comprising at least the carrier fordouble-side polishing apparatus according to claim
 8. 14. A double-sidepolishing method for a semiconductor wafer, comprising: arranging thecarrier according to claim 2 between upper and lower turn tables holdingthe semiconductor wafer in a holding hole formed in the carrier; andsandwiching the semiconductor wafer between the upper and lower turntables to perform double-side polishing.
 15. A double-side polishingmethod for a semiconductor wafer, comprising: arranging the carrieraccording to claim 3 between upper and lower turn tables holding thesemiconductor wafer in a holding hole formed in the carrier; andsandwiching the semiconductor wafer between the upper and lower turntables to perform double-side polishing.
 16. A double-side polishingmethod for a semiconductor wafer, comprising: arranging the carrieraccording to claim 4 between upper and lower turn tables holding thesemiconductor wafer in a holding hole formed in the carrier; andsandwiching the semiconductor wafer between the upper and lower turntables to perform double-side polishing.
 17. A double-side polishingmethod for a semiconductor wafer, comprising: arranging the carrieraccording to claim 7 between upper and lower turn tables holding thesemiconductor wafer in a holding hole formed in the carrier; andsandwiching the semiconductor wafer between the upper and lower turntables to perform double-side polishing.
 18. A double-side polishingmethod for a semiconductor wafer, comprising: arranging the carrieraccording to claim 8 between upper and lower turn tables holding thesemiconductor wafer in a holding hole formed in the carrier; andsandwiching the semiconductor wafer between the upper and lower turntables to perform double-side polishing.